1. Technical Field
The present invention relates to phase locked loops and, more particularly, to removing deterministic phase error from fractional-N analog phase locked loops.
2. Description of the Related Art
Phase locked loops (PLLs) are components in many systems, e.g., microprocessors, millimeter-wave radios, and serial links. A fractional-N PLL is a PLL which generates an output frequency having a non-integer or fractional ratio to the input reference frequency. A fractional-N PLL typically achieves this by modulating the division ratio of the PLL's feedback divider in integer steps, so as to achieve an average fractional (non-integer) net division ratio.
Conventional analog fractional-N PLLs use linear charge pumps and analog loop filters. Converting a PLL from an integer-N to fractional-N typically comes at a price of degrading the phase noise and jitter performance of the PLL. In conventional fractional-N PLLs, deterministic noise is added to the PLL, which results in a degradation in phase noise and jitter performance. Previous attempts to remove this deterministic noise have utilized analog intensive cancellation schemes that are difficult to implement in manufacturing processing optimized for designs with significant digital content.
One example of deterministic phase error subtraction involves the use of current digital analog converters (DACs) to subtract sigma-delta noise from the loop filter. However, it is difficult to match the gain of the DAC to the gain of the charge pump. Typically, a slow least-means-squared based calibration scheme is used to calibrate the gain of the cancellation path. DACs are large, inflexible, and slow to calibrate. In another example, a gated ring oscillator is used as a part of a time-to-digital converter, where the ring is frozen between measurements, such that quantization error is recycled. This latter approach results in high pass shaping of the quantization noise.